[coreboot-gerrit] [S] Change in coreboot[master]: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP

[Chris Wang (Code Review)]

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74757 )

Change subject: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP
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vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP

Update UPD structure to align with MDN-FSP.

BUG=b:271704149
BRANCH=none
Test=Build/Boot to ChromeOS

Signed-off-by: Chris Wang 
Change-Id: Id410c40a65c0fd4b9b73cf36dc1f08eba0a3e44c
---
M src/vendorcode/amd/fsp/mendocino/FspmUpd.h
1 file changed, 19 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74757/1

diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
index 391c64b..933a1d6 100644
--- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
@@ -101,8 +101,9 @@
    /** Offset 0x04E1**/	uint32_t                    vrm_maximum_current_limit_mA;
    /** Offset 0x04E5**/	uint32_t                    vrm_soc_current_limit_mA;
    /** Offset 0x04E9**/	uint8_t                     fch_usb_3_port_force_gen1;
-	/** Offset 0x04E9**/	uint8_t                     pwr_on_vary_bl_to_blon;
-	/** Offset 0x04EA**/	uint8_t                     UnusedUpdSpace2[277];
+	/** Offset 0x04EA**/	uint8_t                     pwr_on_vary_bl_to_blon;
+	/** Offset 0x04EB**/	uint8_t                     pwr_down_bloff_to_varybloff;
+	/** Offset 0x04EC**/	uint8_t                     UnusedUpdSpace2[276];
    /** Offset 0x0600**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;