Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31951 )
Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c File src/device/pciexp_device.c:
https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c@470 PS1, Line 470: PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 |
The values you set should be parameters to this function, as you cannot assume them to be the same f […]
what i could see its more over intel specific hence its better to make a softlink and move actual implementation into intel/common someplace as applicable
https://review.coreboot.org/#/c/31951/1/src/include/device/pciexp.h File src/include/device/pciexp.h:
https://review.coreboot.org/#/c/31951/1/src/include/device/pciexp.h@12 PS1, Line 12:
Is there some relation between realtime and register value? […]
yes there is relation.
LTR snoop/non snoop field are like 16 bit registers
0-9: Latency value 10-12: Latency scale [000: Value times 1ns 001: Value times 32ns 010: Value times 1024ns 011 - Value time 32768ns 100 - value times 1048576ns 101 - Value times 33554432ns 110-111 reserved ]
13-15: reserved
so now if you decode 0x1003, latency value is 3 scale is 100 - 1.04ms so LTR value would be = 1.04*3 = 3.14ms