[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]

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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36519 )

Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36519/1/src/soc/intel/cannonlake/fs... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/36519/1/src/soc/intel/cannonlake/fs... 
PS1, Line 277:        params->PchUsb2PhySusPgEnable = 0;
please, no spaces at the start of a line