Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13409
-gerrit
commit e02a488b47b4da011fdf0cd75df58ebc9fef7318 Author: Alexandru Gagniuc alexandrux.gagniuc@intel.com Date: Fri Jan 15 14:52:20 2016 -0800
intel/apollolake_rvp: Take PCI-express devices out of reset
The reset signals for PCIe links are connected to GPIOs. Those need to manually be set to the proper level before PCIe links will work.
Change-Id: I4fbf3d02516fbc651dda709b41bbab120372bee9 Signed-off-by: Alexandru Gagniuc alexandrux.gagniuc@intel.com --- src/mainboard/intel/apollolake_rvp/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c index dc7bc1e..c11a080 100644 --- a/src/mainboard/intel/apollolake_rvp/mainboard.c +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -14,10 +14,19 @@ #include <soc/gpio.h>
/* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ +/* + * GPIOs: + * A tilde (~) before the name means that the signal uses inverted logic. + * PCIE RST signals route to the PWRGOOD(PCIe slot) or PERST0(M2 slot) inputs. + */ static const struct pad_config aplk_rvp_gpios[] = { + PAD_CFG_GPO(GPIO_13, 1, DEEP), /* ~PCIE_SLOT2_RST_N */ + PAD_CFG_GPO(GPIO_15, 1, DEEP), /* ~WIFI_RST_GPIO_N */ PAD_CFG_GPO(GPIO_22, 1, DEEP), /* SATA Direct power */ + PAD_CFG_GPO(GPIO_37, 1, DEEP), /* ~LAN_RST_N */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ + PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ~PCIE_SLOT1_RST_N */ PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */ PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */ PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */