[coreboot-gerrit] Change in ...coreboot[master]: soc/fsp_broadwell_de: Configure serial port UPDs correctly

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33452

Change subject: soc/fsp_broadwell_de: Configure serial port UPDs correctly
......................................................................

soc/fsp_broadwell_de: Configure serial port UPDs correctly

The SerialPortConfigure UPD (among others) was being left unconfigured
when the SoC's integrated UART was not used, leading to serial output
via an SIO-attached UART being disabled upon FSP init.

Ensure that all serial-related UPDs are set correctly regardless of
Kconfig options selected.

Test: Boot BDE-based board and verify SIO serial output continues
past FSP init

Signed-off-by: Matt DeVillier 
Change-Id: I634120648afb094be762093b5f9549c241c5668a
---
M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
1 file changed, 8 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33452/1

diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
index edb313e..63f9a74 100644
--- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
@@ -64,10 +64,17 @@
    		UpdData->SerialPortBaudRate = 11;
    	else if (CONFIG(CONSOLE_SERIAL_115200))
    		UpdData->SerialPortBaudRate = 12;
+	} else {
+		UpdData->SerialPortConfigure = 0;
+		UpdData->SerialPortControllerInit0 = 0;
+		UpdData->SerialPortControllerInit1 = 0;
    }

-	if (!CONFIG(CONSOLE_SERIAL))
+	if (CONFIG(CONSOLE_SERIAL)) {
+		UpdData->SerialPortType = 1;
+	} else {
    	UpdData->SerialPortType = 0;
+	}

UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL;