Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 25: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 50: uint32_t flags; nit: mention `enum pcie_rp_flags` in a comment here?
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 160: CONFIG_MAX_ROOT_PORTS I wonder if we should add a new Kconfig for CPU root ports?
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ro... PS25, Line 32: type suggestion: change this word to pcie_rp_type so the error message is a little more informative