Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37833 )
Change subject: hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon ......................................................................
hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon
In https://review.coreboot.org/c/coreboot/+/37459 (commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset pin control of FPMCU to var/board/ramstage, but does not implement it for dratini/jinlon. So, add it in dratini/jinlon.
BUG=b:146366921 TEST=emerge-hatch coreboot
Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f Signed-off-by: Wisley Chen wisley.chen@quantatw.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/dratini/Makefile.inc M src/mainboard/google/hatch/variants/dratini/gpio.c A src/mainboard/google/hatch/variants/dratini/ramstage.c M src/mainboard/google/hatch/variants/jinlon/Makefile.inc M src/mainboard/google/hatch/variants/jinlon/gpio.c A src/mainboard/google/hatch/variants/jinlon/ramstage.c 6 files changed, 124 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 4ed09c9..0d577cd 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -26,3 +26,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index fd59060..e3b3d8a 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -134,3 +134,32 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dratini/ramstage.c b/src/mainboard/google/hatch/variants/dratini/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index 6e5d883..c57d090 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -25,3 +25,4 @@
bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 12d96d8..2bf97b1 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -110,3 +110,32 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/jinlon/ramstage.c b/src/mainboard/google/hatch/variants/jinlon/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +}