Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39034 )
Change subject: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS switch ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39034/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39034/1//COMMIT_MSG@9 PS1, Line 9: have difference setting
different setting […]
Done
https://review.coreboot.org/c/coreboot/+/39034/1//COMMIT_MSG@12 PS1, Line 12:
What problem is caused? Failed boot? […]
D is 13,A is 10, this is threshold level of DVFS switch policy. EMCP and discrete DDR have different DRAM frequency table. for EMCP DDR, the DRAM frequency are 1600Mbps, 3200Mbps, 3600Mbps, for 1600Mbps auto switch to 3200Mbps need threshold level reach to 0x7,for 3200Mbps auto switch to 3600Mbps need threshold level reach to 0xD, but discrtet DDR, the DRAM frequecy are 1600Mbps, 2400Mbps, 3200Mbps. for 2400Mbps auto switch to 3200Mbps only need threshold level reach to 0xA old setting will make DVFS switch more frequently, it affect the low power only.
https://review.coreboot.org/c/coreboot/+/39034/1//COMMIT_MSG@15 PS1, Line 15: TEST=bootup pass
Before it failed?
ditto