Change subject: soc/intel/tigerlake: Reorganize memory initialization support
......................................................................
Patch Set 8: Code-Review-1
There is currently work ongoing to split TGL and JSL SoC code. Let's wait until that happens to push this in.
Will this takes long time? We need enable DDR4 for deltan PO.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/39865
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Gerrit-Change-Number: 39865
Gerrit-PatchSet: 8
Gerrit-Owner: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Nick Vaccaro
nvaccaro@chromium.org
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Ravishankar Sarawadi
ravishankar.sarawadi@intel.com
Gerrit-Reviewer: Srinidhi N Kaushik
srinidhi.n.kaushik@intel.com
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: Varun Joshi
varun.joshi@intel.com
Gerrit-Reviewer: Varun Joshi
varun.joshi@intel.corp-partner.google.com
Gerrit-Reviewer: Wonkyu Kim
wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-CC: Selma Bensaid
selma.bensaid@intel.com
Gerrit-Comment-Date: Wed, 01 Apr 2020 04:13:57 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment