[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12008

-gerrit

commit a6e8650b1f18e9671c23cc973eb790a153db01ab
Author: Timothy Pearson 
Date:   Fri Jun 26 00:17:10 2015 -0500

northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements

Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  |  8 ++++++++
 src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 16 ++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index fa32901..9593d71 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -5825,7 +5825,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
 static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
    				struct DCTStatStruc *pDCTstat, u8 dct)
 {
+	printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
    mct_ProgramODT_D(pMCTstat, pDCTstat, dct);
+
+	printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }

static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
@@ -5835,6 +5839,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
    u32 dword;
    u32 dev = pDCTstat->dev_dct;

+	printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
    /* FIXME
     * Mainboards need to be able to specify the maximum number of DIMMs installable per channel
     * For now assume a maximum of 2 DIMMs per channel can be installed
@@ -6149,6 +6155,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
    		Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
    	}
    }
+
+	printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }

static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 46a0684..09f86ea 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -188,9 +188,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct)
    u32 dev = pDCTstat->dev_dct;
    u32 val;

+	printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
    do {
    	val = Get_NB32_DCT(dev, dct, 0x98);
    } while (!(val & (1 << DctAccessDone)));
+
+	printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }

static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct)
@@ -235,6 +239,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
    u32 dev = pDCTstat->dev_dct;
    u32 val;

+	printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
    val = Get_NB32_DCT(dev, dct, 0x7c);
    val &= ~0x00ffffff;
    val |= EMRS;
@@ -244,6 +250,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
    do {
    	val = Get_NB32_DCT(dev, dct, 0x7c);
    } while (val & (1 << SendMrsCmd));
+
+	printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }

static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
@@ -553,6 +561,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
    u32 dev = pDCTstat->dev_dct;
    u32 dword;

+	printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
    /*1.Program MrsAddress[10]=1
      2.Set SendZQCmd=1
     */
@@ -569,6 +579,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)

/* 4.Wait 512 MEMCLKs */
    mct_Wait(300);
+
+	printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }

void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
@@ -578,6 +590,8 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
    u32 dword;
    u32 dev = pDCTstat->dev_dct;

+	printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
    if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
    	/* 3.Program F2x[1,0]7C[EnDramInit]=1 */
    	dword = Get_NB32_DCT(dev, dct, 0x7c);
@@ -659,4 +673,6 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
    	Set_NB32_DCT(dev, dct, 0x7C, dword);
    	mct_DCTAccessDone(pDCTstat, dct);
    }
+
+	printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }