Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38624
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................
soc/intel/tigerlake: Configure TCSS setting
Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681
BUG=none BRANCH=none TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 38 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/2