Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )
Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38512/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38512/3//COMMIT_MSG@10 PS3, Line 10: and the size of the MMIO area is 20KB (0x5000).
This explains nothing about the actual change.
Ack
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 185: #if !CONFIG(TPM_CR50)
this MMIO address range is specific for TPM specification and from Intel PCH side, this address does […]
Ack
https://review.coreboot.org/c/coreboot/+/38512/3/src/soc/intel/skylake/acpi/... PS3, Line 190: 0x00005000)
All the #if aside, where is it written that the PCH doesn't decode this range […]
PCH will always decode any valid fixed range memory but as per PCH fixed memory map, i don't see this memory been mentioned