Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47396 )
Change subject: soc/intel/tigerlake: Check TBT & TCSS ports for wake events
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Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47396/1/src/soc/intel/tigerlake/elo...
File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47396/1/src/soc/intel/tigerlake/elo...
PS1, Line 86: SA_DEVFN_TCSS_XHCI
I think that makes sense. It looks like both north and south XHCI have the exact same structure. […]
Done
https://review.coreboot.org/c/coreboot/+/47396/3/src/soc/intel/tigerlake/elo...
File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47396/3/src/soc/intel/tigerlake/elo...
PS3, Line 125: dev_found =
Ooh true, also line 120, those will have to be OR
Done
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