Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33411 )
Change subject: inteltool: add support for CannonPoint-LP ......................................................................
Patch Set 2: Code-Review+1
Reading through the changes, they look good. The largest part, the addition of the GPIO definitions, appears to match the PCH documentation.
I was able to confirm this change makes inteltool --gpio work on a WhiskeyLake U system, the System76 galp3-c.
Adding CannonPoint PCH-H will be a similar task, with many shared GPIOs with PCH-LP.
The reason the P2SB address is required to be hard coded should be mentioned in the commit message - in many systems the P2SB is locked, after reading the FSP source code it appears that the PchSbAccessUnlock UPD setting does this, and it is defaulted to 0: https://github.com/IntelFsp/FSP/blob/master/CoffeeLakeFspBinPkg/Fsp.bsf#L105....
I can't go into more detail about the FSP source code other than it appears to lock the P2SB PCI device until the PCH is reset, and can only be unlocked for a reset cycle by editing the FSP UPD values which is not possible unless you already have the ability to rebuild firmware. In coreboot, we could potentially add this setting to chip.h.
Thankfully the GPIO is still accessible with MMIO even after the sideband PCI device is locked, presumably to allow for drivers and ACPI tables to continue manipulating the GPIO after PCH init.