[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Begin adding FSP support

[Marshall Dawson (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34423

to look at the new patch set (#11).

Change subject: soc/amd/picasso: Begin adding FSP support
......................................................................

soc/amd/picasso: Begin adding FSP support

AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments.  Unlike Arch2008 (a.k.a. v5), it can't be built
without additional source, e.g. in EDK II, and has no entry points
for easy inclusion into a legacy BIOS.

AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.

* Add fsp_memory_init() to romstage.c.  Although Picasso comes out
  of reset with DRAM alive, this call is added to maximize
  compatibility and facilitate internal development.  Future work
  may look at removing it.
* AGESA currently sets up MTRRs, as in most older generations.
  Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver does this step.
* Add chipset_handle_reset() for compatibility.
* Determine the memory map from HOBs passed from AGESA, as reading
  the TOM register is misleading when UMA is below 4GB.

Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
M src/soc/amd/picasso/chip.c
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/hybrid_romstage.c
M src/soc/amd/picasso/include/soc/iomap.h
M src/soc/amd/picasso/memmap.c
M src/soc/amd/picasso/reset.c
M src/soc/amd/picasso/southbridge.c
9 files changed, 120 insertions(+), 61 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/34423/11