[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31386

Change subject: soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz
......................................................................

soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz

In preparation for board padmelon which will use a clock source different
from the one already present in sb_clk_output_48Mhz, change its code to
input the desired clock source and set appropriate register based on this
input.

BUG=b:none.
TEST=Build and boot grunt, test again later with padmelon.

Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 13 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31386/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 3ae6b4a..705fe7a 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -186,6 +186,7 @@
 #define MISC_CLK_CNTL1			0x40
 #define   CG1PLL_FBDIV_TEST		BIT(26)
 #define   OSCOUT1_CLK_OUTPUT_ENB	BIT(2)  /* 0 = Enabled, 1 = Disabled */
+#define   OSCOUT2_CLK_OUTPUT_ENB	BIT(7)  /* 0 = Enabled, 1 = Disabled */

/* XHCI_PM Registers:  0xfed81c00 */
 #define XHCI_PM_INDIRECT_INDEX		0x48
@@ -477,7 +478,7 @@
 void enable_aoac_devices(void);
 void sb_enable_rom(void);
 void configure_stoneyridge_i2c(void);
-void sb_clk_output_48Mhz(void);
+void sb_clk_output_48Mhz(u32 osc);
 void sb_disable_4dw_burst(void);
 void sb_enable(struct device *dev);
 void southbridge_final(void *chip_info);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index c8d66ac..798bcb4 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -389,7 +389,7 @@
    pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
 }

-void sb_clk_output_48Mhz(void)
+void sb_clk_output_48Mhz(u32 osc)
 {
    u32 ctrl;
    u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE
@@ -401,8 +401,16 @@
     */
    ctrl = read32(misc_clk_cntl_1_ptr);

-	/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
-	ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
+	switch (osc) {
+	case 1:
+		ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
+		break;
+	case 2:
+		ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
+		break;
+	default:
+		return; /* do nothing if invalid */
+	}
    write32(misc_clk_cntl_1_ptr, ctrl);
 }