[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )

Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
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Patch Set 6:

(1 comment)

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/61520/comment/f04b9861_5a83a23b 
PS5, Line 1014: 	/*
> > > > Please update the ME BWG to document the expectation for applicable CSE LITE SKU. […]
>
> Also, looks like you have missed to answer my another question about if FSP alway programmed the CF9 global reset lock bit in previous generation SOC platform then how did CSE fw update works ?

CSE firmware update is triggered by coreboot (BIOS) before FSP notify call. BTW, CSE firmware update flow is nothing to do with global reset  which is get triggered by "I/O 0xCF9 write of 06h or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR set". 
BTW, CSE firmware update flow uses the GLOBAL RESET MEI message.