14 Sep
2020
14 Sep
'20
7:03 a.m.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45325 )
Change subject: nb/intel/ironlake: Reserve gap betwen TSEG and BGSM ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... File src/northbridge/intel/ironlake/northbridge.c:
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... PS2, Line 137: it uncacheable, though, for easier MTRR allocation. */
I think we might be talking past each other. This is not a workaround. […]
Oh, I understand now. Thank you.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Gerrit-Change-Number: 45325
Gerrit-PatchSet: 2
Gerrit-Owner: Nico Huber nico.h@gmx.de
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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Gerrit-Comment-Date: Mon, 14 Sep 2020 10:03:56 +0000
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