Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17544
-gerrit
commit 5da9775a3c0842d0eb54733e710d7c2065f2a11e Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sun Nov 20 19:20:16 2016 +0200
intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULT
Untested.
Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/northbridge/intel/fsp_sandybridge/Kconfig | 8 +++++-- src/northbridge/intel/fsp_sandybridge/bootblock.c | 26 ++++++++++++++++++++++ src/northbridge/intel/fsp_sandybridge/early_init.c | 2 -- 3 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index c6d46d1..96b2df5 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -18,16 +18,20 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE bool select CPU_INTEL_FSP_MODEL_206AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT
config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE bool select CPU_INTEL_FSP_MODEL_306AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT
if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
+config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/fsp_sandybridge/bootblock.c" + config VGA_BIOS_ID string default "8086,0106" diff --git a/src/northbridge/intel/fsp_sandybridge/bootblock.c b/src/northbridge/intel/fsp_sandybridge/bootblock.c new file mode 100644 index 0000000..1c1d492 --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/bootblock.c @@ -0,0 +1,26 @@ +#include <arch/io.h> + +/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c index 5ac1ac6..5071def 100644 --- a/src/northbridge/intel/fsp_sandybridge/early_init.c +++ b/src/northbridge/intel/fsp_sandybridge/early_init.c @@ -30,8 +30,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);