Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 49:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 589: duty_delay_reg_convert
RANK0 and RANK1 share the same duty delay, use RANK0 is ok.
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 599: DQS_NUMBER
DQS_NUMBER is for common, dram_param DQS_NUMBER_LP4 is for LP4, keep DQS_NUMBER here.
Ack
https://review.coreboot.org/c/coreboot/+/44710/49/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/49/src/soc/mediatek/mt8192/dr... PS49, Line 595: 0 RANK_0