T Michael Turney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 )
Change subject: sdm845: Add QCLib to RomStage to perform IP init ......................................................................
Patch Set 76:
(4 comments)
https://review.coreboot.org/#/c/25208/76/src/mainboard/google/cheza/chromeos... File src/mainboard/google/cheza/chromeos.fmd:
https://review.coreboot.org/#/c/25208/76/src/mainboard/google/cheza/chromeos... PS76, Line 27: (
nit: flags are normally written without space before the parenthesis (compare COREBOOT(CBFS) above).
Ack
https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/include/soc... File src/soc/qualcomm/sdm845/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/include/soc... PS76, Line 31: 8192
nit: 8K
Ack
https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/soc... File src/soc/qualcomm/sdm845/include/soc/qclib.h:
https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/soc... PS69, Line 52: #define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001
Yeah, it doesn't really matter, it just makes it easier for me because I don't always get the new Qc […]
Just sent yet another email query on this issue and added it to my Daily ToDo list. I will try to have an update Thursday morning as the India team is responsible for these releases.
https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/qclib.c File src/soc/qualcomm/sdm845/qclib.c:
https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/qclib.c@43 PS76, Line 43: if (size < 0)
This must be a different variable that's ssize_t.
Ack Wonder why the compiler didn't alert, must be same size?