[coreboot-gerrit] Change in coreboot[master]: cpu/amd/family_10h-family_15h/bootblock.c: Add basic C bootblock init

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62089 )

Change subject: cpu/amd/family_10h-family_15h/bootblock.c: Add basic C bootblock init
......................................................................

cpu/amd/family_10h-family_15h/bootblock.c: Add basic C bootblock init

Enable PCI MMCONF and LAPIC for delay functions.

Signed-off-by: Michał Żygowski 
Change-Id: I4eab0012f8f1a3ed2a6124c9d0bb9aff8e95777e
---
M src/cpu/amd/family_10h-family_15h/bootblock.c
M src/southbridge/amd/sr5650/Kconfig
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/62089/1

diff --git a/src/cpu/amd/family_10h-family_15h/bootblock.c b/src/cpu/amd/family_10h-family_15h/bootblock.c
index dd9a772..674e596 100644
--- a/src/cpu/amd/family_10h-family_15h/bootblock.c
+++ b/src/cpu/amd/family_10h-family_15h/bootblock.c
@@ -1,14 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <bootblock_common.h>
+#include <amdblocks/amd_pci_mmconf.h>
 #include <arch/bootblock.h>
 #include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>

static uint32_t saved_bist;

asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
 {
    saved_bist = bist;
+
+	enable_pci_mmconf();
+
+	if (CONFIG(UDELAY_LAPIC))
+		enable_lapic();
+
    /* Call lib/bootblock.c main */
    bootblock_main_with_basetime(base_timestamp);
 }
diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig
index 7dff4f6..7d1980a 100644
--- a/src/southbridge/amd/sr5650/Kconfig
+++ b/src/southbridge/amd/sr5650/Kconfig
@@ -15,4 +15,4 @@

config SOUTHBRIDGE_AMD_SR5650
    bool
-
+	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF