Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39865 )
Change subject: soc/intel/tigerlake: Reorganize memory initialization support ......................................................................
soc/intel/tigerlake: Reorganize memory initialization support
This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added.
It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. Additionally, spd_info structure is organized to allow mixed topologies as well.
TEST=Verified that volteer still boots and memory initialization is successful.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 --- M src/mainboard/google/volteer/romstage.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/baseboard/memory.c M src/soc/intel/tigerlake/include/soc/meminit_tgl.h M src/soc/intel/tigerlake/meminit_tgl.c 5 files changed, 219 insertions(+), 145 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39865/1
diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 5d588b2..2a51276 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -17,12 +17,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct mb_lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct lpddr4x_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { - .read_type = READ_SPD_CBFS, - .spd_spec.spd_index = variant_memory_sku(), + .topology = MEMORY_DOWN, + .md_spd_loc = SPD_CBFS, + .cbfs_index = variant_memory_sku(), }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL);
- meminit_lpddr4x_dimm0(mem_cfg, board_cfg, &spd_info, half_populated); + meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index f368d88..8ab4531 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -23,7 +23,7 @@
const struct cros_gpio *variant_cros_gpios(size_t *num);
-const struct mb_lpddr4x_cfg *variant_memory_params(void); +const struct lpddr4x_cfg *variant_memory_params(void); int variant_memory_sku(void);
#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index db2946d..d16de47 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -9,7 +9,7 @@ #include <baseboard/variants.h> #include <gpio.h>
-static const struct mb_lpddr4x_cfg baseboard_memcfg = { +static const struct lpddr4x_cfg baseboard_memcfg = { /* DQ byte map */ .dq_map = { { 0, 1, 2, 3, 4, 5, 6, 7, /* Byte 0 */ @@ -40,7 +40,7 @@ .ect = 0, /* Disable Early Command Training */ };
-const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +const struct lpddr4x_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h index 5573fb7..82d632e 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h @@ -14,35 +14,42 @@
#define BYTES_PER_CHANNEL 2 #define BITS_PER_BYTE 8 -#define DQS_PER_CHANNEL 2 -#define NUM_CHANNELS 8 +#define DQ_PER_CHANNEL (BYTES_PER_CHANNEL * BITS_PER_BYTE)
-struct spd_by_pointer { - size_t spd_data_len; - uintptr_t spd_data_ptr; +#define DQS_PER_CHANNEL 2 + +#define LPDDR4X_CHANNELS 8 + +enum mem_topology { + MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */ };
-enum mem_info_read_type { - NOT_EXISTING, /* No memory in this channel */ - READ_SPD_CBFS, /* Find spd file in CBFS. */ - READ_SPD_MEMPTR /* Find spd data from pointer. */ +enum md_spd_loc { + /* Read SPD from pointer provided to memory location. */ + SPD_MEMPTR, + /* Read SPD using index into spd.bin in CBFS. */ + SPD_CBFS, };
struct spd_info { - enum mem_info_read_type read_type; - union spd_data_by { - /* To identify spd file when read_type is READ_SPD_CBFS. */ - int spd_index; + enum mem_topology topology;
- /* To find spd data when read_type is READ_SPD_MEMPTR. */ - struct spd_by_pointer spd_data_ptr_info; - } spd_spec; + /* SPD info for Memory down topology */ + enum md_spd_loc md_spd_loc; + union { + /* Used for SPD_CBFS */ + uint8_t cbfs_index; + + /* Used for SPD_MEMPTR */ + uintptr_t data_ptr; + size_t data_len; + }; };
/* Board-specific memory configuration information */ -struct mb_lpddr4x_cfg { +struct lpddr4x_cfg { /* DQ mapping */ - uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + uint8_t dq_map[LPDDR4X_CHANNELS][DQ_PER_CHANNEL];
/* * DQS CPU<>DRAM map. Each array entry represents a @@ -51,7 +58,7 @@ * on the memory part, and the values in the array represent which * pin on the CPU that DRAM pin connects to. */ - uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + uint8_t dqs_map[LPDDR4X_CHANNELS][DQS_PER_CHANNEL];
/* * Early Command Training Enable/Disable Control @@ -60,10 +67,7 @@ uint8_t ect; };
-/* Initialize default memory configurations for dimm0-only lpddr4x */ -void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - const struct spd_info *spd, - bool half_populated); +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, + const struct spd_info *spd, bool half_populated);
#endif /* _SOC_MEMINIT_TGL_H_ */ diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit_tgl.c index a0e5107..cc76daf 100644 --- a/src/soc/intel/tigerlake/meminit_tgl.c +++ b/src/soc/intel/tigerlake/meminit_tgl.c @@ -19,145 +19,214 @@ DISABLE_BOTH_DIMMS = 3 };
-#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \ - do { \ - memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \ - &_b_cfg->dq_map[_ch], \ - sizeof(_b_cfg->dq_map[_ch])); \ - memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \ - &_b_cfg->dqs_map[_ch], \ - sizeof(_b_cfg->dqs_map[_ch])); \ - } while (0) +static uint8_t get_dimm_cfg(uintptr_t dimm0, uintptr_t dimm1) +{ + if (dimm0 && dimm1) + return ENABLE_BOTH_DIMMS; + if (!dimm0 && !dimm1) + return DISABLE_BOTH_DIMMS; + if (!dimm1) + return DISABLE_DIMM1; + if (dimm0) + die("Disabling of only dimm0 is not supported!\n"); + + return DISABLE_BOTH_DIMMS; +}
-static void spd_read_from_cbfs(const struct spd_info *spd, - uintptr_t *spd_data_ptr, size_t *spd_data_len) +static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, + uintptr_t spd_dimm1) +{ + mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); + + switch (channel) { + case 0: + mem_cfg->MemorySpdPtr00 = spd_dimm0; + mem_cfg->MemorySpdPtr01 = spd_dimm1; + break; + + case 1: + mem_cfg->MemorySpdPtr02 = spd_dimm0; + mem_cfg->MemorySpdPtr03 = spd_dimm1; + break; + + case 2: + mem_cfg->MemorySpdPtr04 = spd_dimm0; + mem_cfg->MemorySpdPtr05 = spd_dimm1; + break; + + case 3: + mem_cfg->MemorySpdPtr06 = spd_dimm0; + mem_cfg->MemorySpdPtr07 = spd_dimm1; + break; + + case 4: + mem_cfg->MemorySpdPtr08 = spd_dimm0; + mem_cfg->MemorySpdPtr09 = spd_dimm1; + break; + + case 5: + mem_cfg->MemorySpdPtr10 = spd_dimm0; + mem_cfg->MemorySpdPtr11 = spd_dimm1; + break; + + case 6: + mem_cfg->MemorySpdPtr12 = spd_dimm0; + mem_cfg->MemorySpdPtr13 = spd_dimm1; + break; + + case 7: + mem_cfg->MemorySpdPtr14 = spd_dimm0; + mem_cfg->MemorySpdPtr15 = spd_dimm1; + break; + + default: + die("Invalid channel: %d\n", channel); + } +} + +static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int channel, const uint8_t *dq_arr) +{ + uint8_t *dq_upd; + + switch (channel) { + case 0: + dq_upd = mem_cfg->DqMapCpu2DramCh0; + break; + case 1: + dq_upd = mem_cfg->DqMapCpu2DramCh1; + break; + case 2: + dq_upd = mem_cfg->DqMapCpu2DramCh2; + break; + case 3: + dq_upd = mem_cfg->DqMapCpu2DramCh3; + break; + case 4: + dq_upd = mem_cfg->DqMapCpu2DramCh4; + break; + case 5: + dq_upd = mem_cfg->DqMapCpu2DramCh5; + break; + case 6: + dq_upd = mem_cfg->DqMapCpu2DramCh6; + break; + case 7: + dq_upd = mem_cfg->DqMapCpu2DramCh7; + break; + default: + die("Invalid channel: %d\n", channel); + } + + if (dq_arr) + memcpy(dq_upd, dq_arr, DQ_PER_CHANNEL); + else + memset(dq_upd, 0, DQ_PER_CHANNEL); +} + +static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int channel, const uint8_t *dqs_arr) +{ + uint8_t *dqs_upd; + + switch (channel) { + case 0: + dqs_upd = mem_cfg->DqsMapCpu2DramCh0; + break; + case 1: + dqs_upd = mem_cfg->DqsMapCpu2DramCh1; + break; + case 2: + dqs_upd = mem_cfg->DqsMapCpu2DramCh2; + break; + case 3: + dqs_upd = mem_cfg->DqsMapCpu2DramCh3; + break; + case 4: + dqs_upd = mem_cfg->DqsMapCpu2DramCh4; + break; + case 5: + dqs_upd = mem_cfg->DqsMapCpu2DramCh5; + break; + case 6: + dqs_upd = mem_cfg->DqsMapCpu2DramCh6; + break; + case 7: + dqs_upd = mem_cfg->DqsMapCpu2DramCh7; + break; + default: + die("Invalid channel: %d\n", channel); + } + + if (dqs_arr) + memcpy(dqs_upd, dqs_arr, DQS_PER_CHANNEL); + else + memset(dqs_upd, 0, DQS_PER_CHANNEL); +} + +static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) { struct region_device spd_rdev; - size_t spd_index = spd->spd_spec.spd_index;
- printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + printk(BIOS_DEBUG, "SPD INDEX = %d\n", index); + if (get_spd_cbfs_rdev(&spd_rdev, index) < 0) die("spd.bin not found or incorrect index\n");
- *spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
- *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + *len = region_device_sz(&spd_rdev); + *data = (uintptr_t)rdev_mmap_full(&spd_rdev); }
-static void get_spd_data(const struct spd_info *spd, - uintptr_t *spd_data_ptr, size_t *spd_data_len) +static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *len) { - if (spd->read_type == READ_SPD_MEMPTR) { - *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; - *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + if (info->md_spd_loc == SPD_MEMPTR) { + *data = info->data_ptr; + *len = info->data_len; return; }
- if (spd->read_type == READ_SPD_CBFS) { - spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); - return; + if (info->md_spd_loc != SPD_CBFS) { + die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); }
- die("no valid way to read SPD info"); + read_spd_from_cbfs(info->cbfs_index, data, len); }
-static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - bool half_populated) -{ - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3); - - if (half_populated) - return; - - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6); - MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7); -} - -static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - uintptr_t spd_data_ptr, - bool half_populated) -{ - uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ - - /* Channel 0 */ - mem_cfg->Reserved9[0] = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - mem_cfg->MemorySpdPtr01 = 0; - - /* Channel 1 */ - mem_cfg->Reserved9[1] = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_data_ptr; - mem_cfg->MemorySpdPtr03 = 0; - - /* Channel 2 */ - mem_cfg->Reserved9[2] = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_data_ptr; - mem_cfg->MemorySpdPtr05 = 0; - - /* Channel 3 */ - mem_cfg->Reserved9[3] = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_data_ptr; - mem_cfg->MemorySpdPtr07 = 0; - - if (half_populated) { - printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); - dimm_cfg = DISABLE_BOTH_DIMMS; - spd_data_ptr = 0; - } - - /* Channel 4 */ - mem_cfg->Reserved9[4] = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_data_ptr; - mem_cfg->MemorySpdPtr09 = 0; - - /* Channel 5 */ - mem_cfg->Reserved9[5] = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_data_ptr; - mem_cfg->MemorySpdPtr11 = 0; - - /* Channel 6 */ - mem_cfg->Reserved9[6] = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_data_ptr; - mem_cfg->MemorySpdPtr13 = 0; - - /* Channel 7 */ - mem_cfg->Reserved9[7] = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_data_ptr; - mem_cfg->MemorySpdPtr15 = 0; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); -} - -/* Initialize onboard memory configurations for lpddr4x */ -void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, - const struct mb_lpddr4x_cfg *board_cfg, - const struct spd_info *spd, - bool half_populated) +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, + const struct spd_info *info, bool half_populated)
{ - size_t spd_data_len; - uintptr_t spd_data_ptr; + size_t spd_len; + uintptr_t spd_data; + int i;
- get_spd_data(spd, &spd_data_ptr, &spd_data_len); - print_spd_info((unsigned char *)spd_data_ptr); + if (info->topology != MEMORY_DOWN) + die("LPDDR4x only support memory-down topology.\n");
- mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr, - half_populated); - - /* LPDDR4 does not allow interleaved memory */ + /* LPDDR4x does not allow interleaved memory */ mem_cfg->DqPinsInterleaved = 0; mem_cfg->ECT = board_cfg->ect; mem_cfg->MrcSafeConfig = 0x1; + + read_md_spd(info, &spd_data, &spd_len); + print_spd_info((unsigned char *)spd_data); + + mem_cfg->MemorySpdDataLen = spd_len; + + for (i = 0; i < LPDDR4X_CHANNELS; i++) { + if (half_populated && (i >= (LPDDR4X_CHANNELS / 2))) { + /* + * If memory is half-populated, then upper half of the channels + * need to be left empty. + */ + init_spd_upds(mem_cfg, i, 0, 0); + init_dq_upds(mem_cfg, i, NULL); + init_dqs_upds(mem_cfg, i, NULL); + } else { + init_spd_upds(mem_cfg, i, spd_data, 0); + init_dq_upds(mem_cfg, i, board_cfg->dq_map[i]); + init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i]); + } + } }