[coreboot-gerrit] [S] Change in coreboot[master]: src/soc/intel/alderlake: Add IBECC to Alderlake

[Angel Pons (Code Review)]

Attention is currently required from: Paul Menzel, Christian Walter, Tim Wawrzynczak, Maximilian Brune, Lean Sheng Tan, David Milosevic.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68756 )

Change subject: src/soc/intel/alderlake: Add IBECC to Alderlake
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Patch Set 5: Code-Review+1

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/68756/comment/b91dd1b9_2284d251 
PS5, Line 7: src/
Drop `src/`

https://review.coreboot.org/c/coreboot/+/68756/comment/985feb7a_c5d54379 
PS5, Line 10: Board
> board?

Without capitalizing `b`? +1

https://review.coreboot.org/c/coreboot/+/68756/comment/df2658e6_32b6207d 
PS5, Line 11:
> Please elaborate. Is the FSP doing that?

Yes, it's done as part of MRC.
> Please add how and with what memory modules you tested this.

How about mentioning this in CB:68783 instead?

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/68756/comment/8d094b0a_ee491bd7 
PS5, Line 372: !!config->ibecc.enable
It's a `bool` already