build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/8/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/8/src/soc/intel/alderlake/rom... PS8, Line 38: if(config->PcieRp[i].clkreq == 0xff) space required before the open parenthesis '('