[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Subrata Banik (Code Review)]

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Vikrant L Jadeja.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 11:

(2 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/85454/comment/b1fb2688_f732281e?usp... :
PS11, Line 420: SOC_INTEL_PANTHERLAKE_SIGN_OF_LIFE
can you please rely on https://review.coreboot.org/c/coreboot/+/83770 Kconfig.

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85454/comment/1ac73feb_e653dae4?usp... :
PS11, Line 375: 
how about someone still using CSE sync in romstage ? (like non-CrOS usecase). we might still support there workflow ?

can you please take a look at MTL flow ?