[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Make MAD_DIMM_* registers indexed

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46362 )

Change subject: nb/intel/haswell: Make MAD_DIMM_* registers indexed
......................................................................

nb/intel/haswell: Make MAD_DIMM_* registers indexed

This allows using the macro in a loop, for instance.

Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46362
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/haswell/registers/mchbar.h
2 files changed, 5 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index aaeaadf..7fd6b3f 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -65,8 +65,8 @@
    int i;

addr_decoder_common = MCHBAR32(MAD_CHNL);
-	addr_decode_chan[0] = MCHBAR32(MAD_DIMM_CH0);
-	addr_decode_chan[1] = MCHBAR32(MAD_DIMM_CH1);
+	addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0));
+	addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1));

printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
           (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
@@ -227,8 +227,8 @@

memset(mem_info, 0, sizeof(struct memory_info));

-	addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
-	addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
+	addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0));
+	addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1));

ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;

diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index d6e59ab..60e16e0 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -5,9 +5,7 @@

/* Register definitions */
 #define MAD_CHNL		0x5000 /* Address Decoder Channel Configuration */
-#define MAD_DIMM_CH0		0x5004 /* Address Decode Channel 0 */
-#define MAD_DIMM_CH1		0x5008 /* Address Decode Channel 1 */
-#define MAD_DIMM_CH2		0x500c /* Address Decode Channel 2 (unused on HSW) */
+#define MAD_DIMM(ch)		(0x5004 + (ch) * 4)
 #define MC_INIT_STATE_G		0x5030
 #define MRC_REVISION		0x5034 /* MRC Revision */