Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55363 )
Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver ......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55363/comment/156af108_4dde14f8 PS2, Line 8: Please start by stating the problem.
https://review.coreboot.org/c/coreboot/+/55363/comment/ffeb9e6f_ebfe9881 PS2, Line 9: This is required as part : of the HECI Interface initialization in order to put the host and CSE into : a known good state for communication. Please reference the specification.
https://review.coreboot.org/c/coreboot/+/55363/comment/f43f3ab6_9cd10b14 PS2, Line 15: Is there bug for this?
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/55363/comment/4eae7dac_a3b41231 PS2, Line 104: makes make
https://review.coreboot.org/c/coreboot/+/55363/comment/460c1ba5_cf6ca512 PS2, Line 104: Triggers Imperative mood: Trigger.
https://review.coreboot.org/c/coreboot/+/55363/comment/db11a750_e57695e0 PS2, Line 105: heci_reset(); How much time does this take? (Please also mention that in the commit message.)