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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
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Patch Set 41: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48340/comment/a8a2c6b0_84e688b9
PS41, Line 9: Refactor PCIE port config structure. Make it easier to map from schematic.
: We don't have to convert the PCIE ports RP number and CLK source in devicetree.
: All the convert will be done by SoC level.
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