HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5959
-gerrit
commit ff44b9abc05aa2f0f318071e76719df40dd126ce Author: Elyes HAOUAS ehaouas@noos.fr Date: Mon Jun 9 07:41:47 2014 +0200
Lenovo t60 & x60: use defined GPIO's
Change-Id: I18fcd32bc26df4ca0dd643068637d3bb0eef7423 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/lenovo/t60/romstage.c | 16 ++++++++-------- src/mainboard/lenovo/x60/romstage.c | 22 +++++++++++----------- 2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..117f4b0 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -60,16 +60,16 @@ void setup_ich7_gpios(void) 38: PLANARID2 39: PLANARID3 */ - outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x1f48f7c2, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0xe0e0ffc3, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0xfbfefb7d, DEFAULT_GPIOBASE + GP_LVL); /* Output Control Registers */ - outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + outl(0x00040000, DEFAULT_GPIOBASE + GPO_BLINK); /* Input Control Registers */ - outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100f0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x000000f1, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x000300a3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + outl(0x000039ff, DEFAULT_GPIOBASE + GPI_INV); + outl(0x000100f0, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x000000f1, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0x000300a3, DEFAULT_GPIOBASE + GP_LVL2); }
static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..4f3ef88 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -67,16 +67,16 @@ void setup_ich7_gpios(void) * 48: FWH_TBL# */
- outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xfbf6ddfd, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x1f40f7c2, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0xfbf6ddfd, DEFAULT_GPIOBASE + GP_LVL); /* Output Control Registers */ - outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + outl(0x00040000, DEFAULT_GPIOBASE + GPO_BLINK); /* Input Control Registers */ - outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100f2, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ + outl(0x000039ff, DEFAULT_GPIOBASE + GPI_INV); + outl(0x000100f2, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x000000f0, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0x00030043, DEFAULT_GPIOBASE + GP_LVL); }
static void ich7_enable_lpc(void) @@ -317,9 +317,9 @@ void main(unsigned long bist) ram_check(0x00000000, 0x000a0000); ram_check(0x00100000, tom); } -#endif -#endif -#endif +#endif /* !CONFIG_HAVE_ACPI_RESUME */ +#endif /* CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 */ +#endif /* CONFIG_DEBUG_RAM_SETUP */
MCHBAR16(SSKPD) = 0xCAFE;