Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30949 )
Change subject: mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec ......................................................................
mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Sarien EVT TouchScreen: 380.7 KHz TouchPad: 379.3 KHz H1: 392.2 KHz
BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope
Signed-off-by: Dtrain Hsu dtrain_hsu@compal.corp-partner.google.com Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Reviewed-on: https://review.coreboot.org/c/30949 Reviewed-by: Lijian Zhao lijian.zhao@intel.com Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 6 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Lijian Zhao: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 4334c45..59f1f30 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -81,17 +81,19 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 190, + .fall_time_ns = 120, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 176, - .fall_time_ns = 15, + .rise_time_ns = 52, + .fall_time_ns = 110, }, .i2c[4] = { .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 280, - .fall_time_ns = 90, + .rise_time_ns = 36, + .fall_time_ns = 99, }, }"