Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33623 )
Change subject: superio/fintek: Add f81803a ......................................................................
Patch Set 7:
This whole code has wrong things, and I was not aware (and apparently neither was Marc, who started the SIO code). There's a lot to study before I make any change. Anyway, thanks for pointing it out. Is there any document I can use for reference?
The documentation is sadly rather thin at the moment. I'd suggest having a look at the SIO part of for example the device tree of asrock/h81m-hds. In line 111 the chip gets selected and in line 148 the 2e.b means the ldn 0xb of pnp device at io address 0x2e gets enabled (the upper 8 bit select the bit number in the enable register (0x30) of the selected ldn. in the next line the first io base address for that ldn gets set, in the next line the second one and in the line after that the irq. th io statement also tells the memory allocator to reserve that memory region; it also uses the masks from the corresponding superio.c. iirc you can only configure things in the devicetree that are mentioned in the pnp_info struct array. some components have a chip.h file and the setting from there can also be configured in devicetree.
apart from the commented line for the WDT the patch set 6 was good and should probably work fine if the resources for the hwm get configured in the devicetree of the board.
during the build process util/sconfig processes the devicetree into the static.c (or .h? not sure on that) file that resides somewhere in the build directory