Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 112 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/1
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 3a06a8c..9d98637 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -66,21 +66,6 @@ southbridge_configure_default_intmap();
static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -135,8 +120,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } }
@@ -186,6 +171,8 @@
setup_pch_gpios(&mainboard_gpio_map);
+ pch_setup_cir(NEHALEM_MOBILE); +
/* This should probably go away. Until now it is required * and mainboard specific diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 5a4a9f1..a426d89 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -61,21 +61,6 @@ southbridge_configure_default_intmap();
static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -131,8 +116,8 @@ unsigned i;
for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } }
@@ -181,6 +166,8 @@
setup_pch_gpios(&mainboard_gpio_map);
+ pch_setup_cir(NEHALEM_MOBILE); + /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f..97565d6 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c
endif diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c new file mode 100644 index 0000000..5628bc5 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include "pch.h" + +/* This set up magic Chipset Initialization Registers */ + +void pch_setup_cir(int chipset_type) +{ + printk(BIOS_DEBUG, "Setting up Chipset Initialization registers\n"); + + uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + struct cpuinfo_x86 c; + + RCBA32(CIR7) = 0xf; + + switch (lpc_id) { + case 0x3b01: + case 0x3b03: + case 0x3b05: + case 0x3b07: + case 0x3b09: + case 0x3b0b: + case 0x3b0d: + case 0x3b0f: + RCBA32_AND_OR(CIR6, 0xff7ffff, 0x600000); + break; + } + + if (chipset_type == NEHALEM_DESKTOP) + pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); + + pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); + + RCBA32(CIR8) = 0x4000000; + pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300); + RCBA32(0x3318) = 0x1020000; /* undocumented */ + get_fms(&c, cpuid_eax(1)); + if (c.x86_model == 0x1e) { + /* Lynnfield/Clarksfield */ + RCBA32(CIR13) = 0xfffff; + RCBA32(CIR14) = 0x61080; + RCBA32(CIR16) = 0x7f8fdf80; + RCBA32(CIR18) = 0; /* Does not match EDS */ + RCBA32(CIR19) = 0x20002; + RCBA32(CIR20) = 0x44b00; + RCBA32(CIR21) = 0x6002000; + /* Program this register after all registers in the + * 3330-33D3 range and D31:F0:A9h are already programmed + */ + RCBA32(CIR22) = 0x20000; + + } else if (c.x86_model == 0x1f || c.x86_model == 0x25) { + /* Auburndale/Havendale + Arrandale/Clarkdale */ + RCBA32(CIR10) = 0xfffff; + RCBA32(CIR15) = 0x7f8fdfff; + RCBA32(CIR17) = 0x3900; + RCBA32(CIR19) = 0x10000; + RCBA32(CIR20) = 0x1004b; + RCBA32(CIR21) = 0x6000008; + /* Program this register after all registers in the + * 3330-33D3 range and D31:F0:A9h are already programmed + */ + RCBA32(CIR22) = 0x10000; + } else { + die("unsupported CPU!\n"); + } +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index ee0f9ad..bc194ac 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@
void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void pch_setup_cir(int chipset_type);
#ifndef __ROMCC__ #include <device/device.h> @@ -104,6 +105,9 @@ #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20)
+#define CIR4 0xa9 +#define PMIR 0xac + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) @@ -352,6 +356,22 @@ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8
+#define CIR6 0x2024 +#define CIR7 0x3314 +#define CIR8 0x3324 +#define CIR9 0x3330 +#define CIR10 0x3340 +#define CIR13 0x3350 +#define CIR14 0x3368 +#define CIR15 0x3378 +#define CIR16 0x3388 +#define CIR17 0x33a0 +#define CIR18 0x33a8 +#define CIR19 0x33c0 +#define CIR20 0x33cc +#define CIR21 0x33d0 +#define CIR22 0x33d4 + #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR))