[coreboot-gerrit] Change in ...coreboot[master]: cpu/intel/model_2065x: Put stage cache in TSEG

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/26298

to look at the new patch set (#42).

Change subject: cpu/intel/model_2065x: Put stage cache in TSEG
......................................................................

cpu/intel/model_2065x: Put stage cache in TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_2065x/Makefile.inc
M src/cpu/intel/model_2065x/model_2065x.h
A src/cpu/intel/model_2065x/stage_cache.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/nehalem/ram_calc.c
6 files changed, 63 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/26298/42