[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82371eb: Support reconfiguring GPO22/23

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38352 )

Change subject: sb/intel/i82371eb: Support reconfiguring GPO22/23
......................................................................

sb/intel/i82371eb: Support reconfiguring GPO22/23

XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not
required. Turns out asus/p2b-ls is using them to control termination
for the onboard SCSI buses. Add support to allow this reconfiguration.

Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38352
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
---
M src/southbridge/intel/i82371eb/chip.h
M src/southbridge/intel/i82371eb/isa.c
2 files changed, 9 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 28975a2..9862082 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -28,6 +28,9 @@
    int ide1_drive1_udma33_enable:1;
    int ide_legacy_enable:1;
    int usb_enable:1;
+	int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */
+	int gpo22:1;
+	int gpo23:1;
    /* acpi */
    u32 gpo; /* gpio output default */
    u8 lid_polarity;
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index bb88f7d..a57d61a 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -28,6 +28,7 @@
 #include <arch/acpigen.h>
 #endif
 #include "i82371eb.h"
+#include "chip.h"

#if CONFIG(IOAPIC)
 static void enable_intel_82093aa_ioapic(void)
@@ -63,6 +64,7 @@
 static void isa_init(struct device *dev)
 {
    u32 reg32;
+	struct southbridge_intel_i82371eb_config *sb = dev->chip_info;

/* Initialize the real time clock (RTC). */
    cmos_init(0);
@@ -80,7 +82,10 @@
     */
    reg32 = pci_read_config32(dev, GENCFG);
    reg32 |= ISA;	/* Select ISA, not EIO. */
-	pci_write_config16(dev, GENCFG, reg32);
+
+	/* Some boards use GPO22/23. Select it if configured. */
+	reg32 = ONOFF(sb->gpo22_enable, reg32, GPO2223);
+	pci_write_config32(dev, GENCFG, reg32);

/* Initialize ISA DMA. */
    isa_dma_init();