[coreboot-gerrit] Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes

[Werner Zeh (Code Review)]

Attention is currently required from: Mario Scheithauer, Werner Zeh.
Hello build bot (Jenkins), Mario Scheithauer,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62698

to look at the new patch set (#2).

Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
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mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes

DDR4 SPD data needs to be 512 byte to comply with the spec.

Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.

This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.

Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62698/2