[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83205?usp=email )

Change subject: mb/google/brask/var/bujia: Configure Serial IO UARTs Mode
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mb/google/brask/var/bujia: Configure Serial IO UARTs Mode

This patch configures Serial IO UARTs mode as below.

UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design.

BUG=b:338917836
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38
Signed-off-by: Shon Wang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205
Reviewed-by: Eric Lai 
Reviewed-by: Derek Huang 
Reviewed-by: Varshit Pandya 
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  Derek Huang: Looks good to me, approved
  build bot (Jenkins): Verified
  Varshit Pandya: Looks good to me, but someone else must approve
  Eric Lai: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb
index 252d82f..4255296 100644
--- a/src/mainboard/google/brya/variants/bujia/overridetree.cb
+++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb
@@ -46,6 +46,12 @@
    	[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
    }"

+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
    register "ddi_ports_config" = "{
    	[DDI_PORT_A] = DDI_ENABLE_HPD,
    	[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,