Attention is currently required from: Shelley Chen, Martin Roth, Paul Menzel, Julius Werner, mturney mturney. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
Patch Set 33:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45205/comment/e778b91e_7c2bf827 PS15, Line 8:
Hey Ravi, I don't see the commit message updated in this latest patchset. […]
Done
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/45205/comment/569824d5_b2b9653e PS24, Line 8: #define SSRAM_END(addr) SYMBOL(essram, addr)
addressed
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/08886646_8b331670 PS24, Line 42: FMAP_CACHE(0x1485B400, 2K)
I don't see CBFS_MCACHE in the latest patchset.
Done
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/24f07dc6_0834b7e9 PS6, Line 9: int qclib_soc_blob_load(void)
Ravi, did you end up refactoring this out as Julius suggested?
sorry for late response, i will acknowledge, the difference is limits config changes i need to remove from sc7280. once confirm with internal team i will move to common code.
File src/soc/qualcomm/sc7280/qclib.c:
https://review.coreboot.org/c/coreboot/+/45205/comment/0f63751a_fe0791bb PS24, Line 12: ssize_t ssize;
I still don't see this correction?
Done
https://review.coreboot.org/c/coreboot/+/45205/comment/48d8f287_11414258 PS24, Line 15: size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg",
addressed
Done