Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34897 )
Change subject: arch/x86: Simplified postcar WB MTRR setup ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34897/1/src/soc/intel/skylake/memma... File src/soc/intel/skylake/memmap.c:
https://review.coreboot.org/c/coreboot/+/34897/1/src/soc/intel/skylake/memma... PS1, Line 317: /* Do some magic alignments */
Why are we doing anything magic? FWIW, we can't lay down a MTRR over potential holes needed in the m […]
Can you pinpoint me to cases/platforms where such holes are required, between TSEG and cbmem_top(), before we reprogram these MTRRs again? MTRR reprogramming used to happen early in PARALLEL_MP, but I do see it may be delayed until payload entry.
Many platforms already do this and select "a suitable alignment somewhere higher than cbmem_top()". Aligning wb_end downwards relaxes us from having any alignment requirement on the implementation on cbmem_top(), which is somewhat convoluted for Intel implementations with EBDA located near TOLM.