[coreboot-gerrit] Change in coreboot[master]: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every tigerlake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e..22c1b2a 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,10 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* USB4/TBT */
+	for (i = 0; i < 4; i++)
+		params->ITbtPcieRootPortEn[i] = 1;
+
    mainboard_silicon_init_params(params);
 }

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index fc3155f..0d11306 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -129,6 +129,13 @@
    config = config_of_soc();

soc_memory_init_params(m_cfg, config);
+
+	/* USB4/TBT */
+	m_cfg->TcssItbtPcie0En = 1;
+	m_cfg->TcssItbtPcie1En = 1;
+	m_cfg->TcssItbtPcie2En = 1;
+	m_cfg->TcssItbtPcie3En = 1;
+
    mainboard_memory_init_params(mupd);
 }