Attention is currently required from: Alexander Couzens, Angel Pons, Evgeny Zinoviev, Kevin Keijzer.
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81882?usp=email )
Change subject: SNB/BD82x6x boards: Remove old USB configurations ......................................................................
SNB/BD82x6x boards: Remove old USB configurations
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/asrock/b75m-itx/Makefile.mk D src/mainboard/asrock/b75m-itx/early_init.c M src/mainboard/asrock/b75pro3-m/early_init.c M src/mainboard/asrock/h77pro4-m/early_init.c M src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c M src/mainboard/asus/maximus_iv_gene-z/early_init.c M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c M src/mainboard/biostar/th61-itx/Makefile.mk M src/mainboard/compulab/intense_pc/early_init.c M src/mainboard/dell/snb_ivb_workstations/early_init.c M src/mainboard/gigabyte/ga-b75m-d3h/early_init.c M src/mainboard/gigabyte/ga-h61m-series/early_init.c M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/early_southbridge.c D src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/dq67sw/early_init.c M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/l520/Makefile.mk D src/mainboard/lenovo/l520/early_init.c M src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420s/early_init.c M src/mainboard/lenovo/t430/early_init.c M src/mainboard/lenovo/x220/Makefile.mk M src/mainboard/lenovo/x220/devicetree.cb D src/mainboard/lenovo/x220/variants/x1/romstage.c D src/mainboard/lenovo/x220/variants/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/sapphire/pureplatinumh61/early_init.c M src/northbridge/intel/sandybridge/chip.h M src/southbridge/intel/bd82x6x/pch.h 62 files changed, 0 insertions(+), 941 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81882/1
diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index fc4b215..8eeb482 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -1,24 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, /* USB HUB 1 */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 1, 0, -1 }, /* USB HUB 2 */ - { 1, 0, -1 }, /* Camera */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ -};
void mb_get_spd_map(struct spd_info *spdi) { diff --git a/src/mainboard/asrock/b75m-itx/Makefile.mk b/src/mainboard/asrock/b75m-itx/Makefile.mk index d1b484d..ae57dab 100644 --- a/src/mainboard/asrock/b75m-itx/Makefile.mk +++ b/src/mainboard/asrock/b75m-itx/Makefile.mk @@ -3,6 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c
-bootblock-y += early_init.c -romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c deleted file mode 100644 index b70794a..0000000 --- a/src/mainboard/asrock/b75m-itx/early_init.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, - {1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6}, -}; diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 4052b6f..1ffd896 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -8,23 +8,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c index 4637378..df8f043 100644 --- a/src/mainboard/asrock/h77pro4-m/early_init.c +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -21,23 +21,6 @@ CPU_FAN_HEADER_BOTH };
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - /* * The tachometer signal that goes to CPUFANIN of the Super I/O is set via * GPIOs. diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c index 50e225a..bec2f6d 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c @@ -10,23 +10,6 @@ #define SIO_DEV PNP_DEV(SIO_PORT, 0) #define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(SIO_DEV); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c index 5f5c684..2217a6c 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c @@ -7,23 +7,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c index 404a850..8f716da 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c @@ -9,23 +9,6 @@ #define GLOBAL_DEV PNP_DEV(0x2e, 0) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c index 1c8d844..d7cd486 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Enable UART */ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c index e76e109..dc00ec3 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index ed593f6..bd741c3 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -6,23 +6,6 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h>
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 4052cf4..e9b97bc 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,11 +7,6 @@ register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
- register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" # 4 bit switch mask. 0=not switchable, 1=switchable # Means once it's loaded the OS, it can swap ports # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c index 79b67f0..1e21f20 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c index 89f9eee..056dfd4 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 47c5cb3..6897658 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -12,24 +12,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - {1, 2, 0}, /* Port 0: USB3 front internal header, top */ - {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ - {1, 2, 1}, /* Port 2: USB3 rear, top */ - {1, 2, 1}, /* Port 3: USB3 rear, bottom */ - {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ - {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ - {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ - {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ - {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ - {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ - {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ - {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ - {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ - {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index c15767b..25e098d4d 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -1,11 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index cec5070..4940b54 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -14,24 +14,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ - { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ - { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ - { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ - { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ - { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ - { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ - { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ - { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ - { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ - { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ - { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ - { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ - { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index 1a011c3..265bada 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -1,11 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {0, 5, 0x0080}, {0, 6, 0x0080} - }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index c16b055..290523f 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -11,23 +11,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 2, 0 }, - { 1, 2, 0 }, - { 1, 2, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 2, 2 }, - { 1, 2, 3 }, - { 1, 2, 3 }, - { 1, 2, 4 }, - { 1, 0, 4 }, - { 1, 2, 6 }, - { 1, 2, 5 }, - { 1, 2, 5 }, - { 1, 2, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 89f9eee..056dfd4 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/biostar/th61-itx/Makefile.mk b/src/mainboard/biostar/th61-itx/Makefile.mk index 33b55d2..51125d3 100644 --- a/src/mainboard/biostar/th61-itx/Makefile.mk +++ b/src/mainboard/biostar/th61-itx/Makefile.mk @@ -5,5 +5,3 @@
ramstage-y += hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index f5859e9..4a4308e 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -8,23 +8,6 @@
#define SIO_PORT 0x164e
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/dell/snb_ivb_workstations/early_init.c b/src/mainboard/dell/snb_ivb_workstations/early_init.c index 4a381df..9ddbaf9 100644 --- a/src/mainboard/dell/snb_ivb_workstations/early_init.c +++ b/src/mainboard/dell/snb_ivb_workstations/early_init.c @@ -9,23 +9,6 @@
#include <baseboard/sch5545_ec.h>
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 6, 0 }, - { 1, 6, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 6, 3 }, - { 1, 6, 3 }, - { 1, 6, 4 }, - { 1, 6, 4 }, - { 1, 6, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 6, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 8fd6f98..eea5b20 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -39,20 +39,3 @@ ite_reg_write(IT8728F_EC, 0x63, 0x20); ite_reg_write(IT8728F_EC, 0x30, 0x01); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, -}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/early_init.c b/src/mainboard/gigabyte/ga-h61m-series/early_init.c index 6f9109a..80a3f0f 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-series/early_init.c @@ -9,23 +9,6 @@ #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(0x2e, 0x01)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { if (!CONFIG(NO_UART_ON_SUPERIO)) { diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index a001f73..3a386c6 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -25,22 +25,6 @@ # Force double refresh rate register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE"
- register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0080 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref peg10 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index f63d3c3..8d07a38 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -44,24 +44,6 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, -1 }, /* P2: Camera (no OC) */ - { 0, 0, -1 }, /* P3: Empty */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 0, 0, -1 }, /* P8: Empty */ - { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ - { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 39b8452..ed49d16 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -22,22 +22,6 @@ # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
- register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index e40531d..2d20ac0 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -63,24 +63,6 @@ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, -1 }, /* P3: SDCARD (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 1, 0, -1 }, /* P5: WWAN (no OC) */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: Camera (no OC) */ - { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ - { 0, 0, -1 }, /* P10: Empty */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { /* LINK has 2 channels of memory down */ diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index da7c388..ea36b9e 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -22,22 +22,6 @@ # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
- register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref igd on end # vga controller diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f91b7d9..077cb64 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -50,22 +50,3 @@ { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 1, 0, -1 }, /* P10: Camera (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 0c029fa..ccbfa31 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -22,22 +22,6 @@ # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
- register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 1, 0x0000 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 1, 0x0000 }, - { 0, 1, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 5, 0x0040 },}" - register "usb3.mode" = "2" # Auto register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1 register "usb3.preboot_support" = "0" # No PreOS boot support diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e6e6227..178d270 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -90,21 +90,3 @@ early_ec_init(); } } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled USB oc pin length */ - {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, /* P2: Empty */ - {1, 0, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, /* P6: Empty */ - {0, 0, 0}, /* P7: Empty */ - {0, 0, 0}, /* P8: Empty */ - {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, /* P10: Empty */ - {0, 0, 0}, /* P11: Empty */ - {0, 0, 0}, /* P12: Empty */ - {1, 0, -1}, /* P13: Bluetooth (no OC) */ -}; diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 46624fb..617cca6 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -15,22 +15,6 @@ register "max_mem_clock_mhz" = "666" register "spd_addresses" = "{0x50, 0, 0x51, 0}"
- register "usb_port_config" = "{ - {1, 0, 0x0040}, - {1, 0, 0x0040}, - {1, 1, 0x0040}, - {1, 1, 0x0040}, - {1, 2, 0x0040}, - {1, 2, 0x0040}, - {1, 3, 0x0040}, - {0, 3, 0x0040}, - {0, 4, 0x0040}, - {0, 4, 0x0040}, - {0, 5, 0x0040}, - {0, 5, 0x0040}, - {0, 6, 0x0040}, - {0, 6, 0x0040}, }" - device domain 0 on device ref host_bridge on end # Host bridge device ref peg10 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index e0f27ba..a137e35 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -124,8 +124,3 @@ superio_init(); hwm_init(); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { -#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } -#include "usb.h" -}; diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h deleted file mode 100644 index 2469309..0000000 --- a/src/mainboard/intel/dcp847ske/usb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DCP847SKE_USB_H -#define DCP847SKE_USB_H - -USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */ -USB_CONFIG(1, 1, 0), /* back, towards power plug */ -USB_CONFIG(1, 1, 1), /* half-width miniPCIe */ -USB_CONFIG(1, 1, 1), /* full-width miniPCIe */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 3), /* front connector */ -USB_CONFIG(0, 1, 3), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ - -#endif diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c index 14317a6..f7515a5 100644 --- a/src/mainboard/intel/dq67sw/early_init.c +++ b/src/mainboard/intel/dq67sw/early_init.c @@ -1,29 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 0, 0, 5 }, - { 0, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 32bab2c..59e91b2 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -14,22 +14,6 @@ register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0, 0x52, 0}"
- register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 1974713..329f13d 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -47,21 +47,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 0, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 0fc75e9..b5001fb 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -10,21 +10,6 @@ register "usb3.mode" = "3" register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, }"
chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index e514f102..7a23765 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -54,24 +54,6 @@ { }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ - { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ -}; - void mainboard_early_init(int s3resume) { /* Enable PEG10 (1x16) */ diff --git a/src/mainboard/lenovo/l520/Makefile.mk b/src/mainboard/lenovo/l520/Makefile.mk index e4b6fbf..7611194 100644 --- a/src/mainboard/lenovo/l520/Makefile.mk +++ b/src/mainboard/lenovo/l520/Makefile.mk @@ -4,5 +4,3 @@ romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c deleted file mode 100644 index ebcd639..0000000 --- a/src/mainboard/lenovo/l520/early_init.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 58e9593..f4396cb6 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -20,23 +20,6 @@ ec_mm_set_bit(0x3b, 4); }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 0, 1 }, - { 1, 1, 2 }, - { 1, 0, 2 }, - { 0, 0, 3 }, - { 0, 1, 3 }, - { 1, 0, 4 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, -}; - static const char *mainboard_spd_names[9] = { "ELPIDA 4GB", "SAMSUNG 4GB", diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index c90221e..79e3cf7 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -31,24 +31,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); }
-// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index e5e95b2..79e3cf7 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -31,23 +31,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 5e397ab..86fcda8 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -33,24 +33,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); }
-/* FIXME: used T530 values here */ -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 2, 3 }, - { 1, 1, -1 }, - { 1, 1, 2 }, - { 1, 0, -1 }, - { 0, 0, -1 }, - { 1, 2, -1 }, - { 1, 0, -1 }, - { 1, 1, 5 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk index b104bb5..7e59707 100644 --- a/src/mainboard/lenovo/x220/Makefile.mk +++ b/src/mainboard/lenovo/x220/Makefile.mk @@ -2,7 +2,6 @@
bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 233f690..927d31a 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -19,22 +19,6 @@ register "ec_present" = "1" # I have an embedded controller register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333
- register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 2, 0x0040 }, - { 1, 2, 0x0040 }, - { 1, 6, 0x0080 }, - { 1, 5, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 7, 0x0080 }, - { 1, 6, 0x0080 },}" - device domain 0 on subsystemid 0x17aa 0x21db inherit
diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c deleted file mode 100644 index 593b7b2..0000000 --- a/src/mainboard/lenovo/x220/variants/x1/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 3 }, - { 0, 0, 3 }, - { 0, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 0, 7 }, - { 1, 1, 7 }, - { 1, 1, 7 }, - { 1, 0, 7 }, -}; diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c deleted file mode 100644 index bd33cef..0000000 --- a/src/mainboard/lenovo/x220/variants/x220/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 1, 3 }, - { 1, 1, -1 }, - { 1, 1, -1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 1, 6 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, - { 1, 1, 7 }, - { 1, 1, 6 }, -}; diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 4a89282..5c26670 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -26,22 +26,6 @@ register "ec_present" = "1" register "max_mem_clock_mhz" = "800"
- register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 2, 0x0080 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 3, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5de8f56..66e3e52 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -8,21 +8,3 @@ /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled / Power / OC PIN */ - { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */ - { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */ - { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */ - { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */ - { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */ - { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */ - { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */ - { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */ - { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */ - { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */ - { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ -}; diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 67773bb..e9f1a46 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -25,21 +25,6 @@ register "usb3.hs_port_switch_mask" = "0xf" register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0080 }, - { 1, 4, 0x0080 }, - { 1, 5, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0080 }, - { 1, 6, 0x0080 }, }"
chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 451c4b7..b791cbc 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,21 +40,3 @@ /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled / Power / OC PIN */ - { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ - { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ - { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ - { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ - { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ - { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ - { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ - { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ - { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ - { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ - { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ -}; diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 5bc15e7..d9ee4b7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -20,22 +20,6 @@ register "ec_present" = "1" register "max_mem_clock_mhz" = "666"
- register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 5b355a2..b82d4d3 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -108,24 +108,6 @@ memcpy(pei_data->ts_addresses, &tsaddr, sizeof(pei_data->ts_addresses)); }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 1, 0 }, /* P0: Port 0 (OC0) */ - { 1, 1, 1 }, /* P1: Port 1 (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 0, 0, -1 }, /* P10: Empty */ - { 1, 0, -1 }, /* P11: Camera (no OC) */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index f9f6ef9..721fd88 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -12,22 +12,6 @@ register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "max_mem_clock_mhz" = "666"
- register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0080 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end
diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 681373c..1310c48 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -91,24 +91,6 @@ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ }
-const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 1, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 1, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; - void bootblock_mainboard_early_init(void) { if (CONFIG(DRIVERS_UART_8250IO)) diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index 8749e49..b4bc111 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -8,20 +8,3 @@ { pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 82e58f6..35e4cf7 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -80,26 +80,6 @@ DDR_REFRESH_RATE_DOUBLE, } ddr_refresh_rate_config;
- /* - * USB Port Configuration: - * [0] = enable - * [1] = overcurrent pin - * [2] = length - * - * Ports 0-7 can be mapped to OC0-OC3 - * Ports 8-13 can be mapped to OC4-OC7 - * - * Port Length - * MOBILE: - * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) - * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) - * DESKTOP: - * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) - * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) - * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) - */ - u16 usb_port_config[16][3]; - struct { /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ u8 mode : 2; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 17ee4b0..8ceadf2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -62,7 +62,6 @@ };
void pch_enable(struct device *dev); -extern const struct southbridge_usb_port mainboard_usb_ports[14];
void early_usb_init(void);