Hello Martin Roth, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34429
to review the following change.
Change subject: _WIP_ soc/amd/picasso: Update all remaining pci_devs ......................................................................
_WIP_ soc/amd/picasso: Update all remaining pci_devs
Unlike older products, many of the Family 17h PCI devices are not on bus 0, and therefore cannot be located using pcidev_on_root(). The PPR (PID #55570, NDA required) shows Bus A and Bus B devices, where 0:8.1 and 0:8.2 are the bridges to them. Also, unlike older products, the bridges are not hidden for the purpose of making devices appear to be on bus 0.
Rework pci_devs.h and other files to account for the new topology.
Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/picasso/include/soc/pci_devs.h 1 file changed, 32 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34429/1
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 28fa99f..de5e446 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -84,7 +84,6 @@ #define PCIE8_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) #define SOC_PCIE8_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC)
- /* Data Fabric functions */ #define DF_DEV 0x18
@@ -116,29 +115,6 @@ #define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) #define SOC_DF_F6_DEVFN _SOC_DEV(DF_DEV, 6)
-/* USB 3.1 */ -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVID 0x15e0 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) -#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) - -/* USB 3.1 */ -#define XHCI1_DEV 0x0 -#define XHCI1_FUNC 4 -#define XHCI1_DEVID 0x15e1 -#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) -#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) -#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 @@ -153,25 +129,48 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
+/* + * Bus A devices + */ + /* Internal Graphics */ -#define GFX_DEV 0x1 +#define GFX_DEV 0x0 #define GFX_FUNC 0 #define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC)
/* HD Audio 0 */ -#define HDA0_DEV 0x1 +#define HDA0_DEV 0x0 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 +#define HDA0_DEVID 0x15de #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC)
-/* HD Audio 1 */ -#define HDA1_DEV 0x9 -#define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a -#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) -#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) + +/* + * Bus B devices + */ + +/* SATA */ +#define SATA_DEV 0x0 +#define SATA_FUNC 0 +#define AHCI_DEVID_MS 0x7901 +#define AHCI_DEVID_AMD 0x7904 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC)
#endif /* __PI_PICASSO_PCI_DEVS_H__ */