[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36032 )

Change subject: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB
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Patch Set 4:

(1 comment)
> Patch Set 4: Code-Review+1
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/36032/4/src/soc/intel/cannonlake/Kc... 
File src/soc/intel/cannonlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/36032/4/src/soc/intel/cannonlake/Kc... 
PS4, Line 128: sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
> please respect the maximum line length

This is within the current limit on the length of lines which is 96 columns.
https://doc.coreboot.org/coding_style.html [Breaking long lines and strings].