Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42190 )
Change subject: nb/intel/i945: Use PCI bitwise ops ......................................................................
nb/intel/i945: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Getac P470 does not change
Change-Id: I181f69372829cf712fd72887b5f2c7134bfcf15a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c 3 files changed, 39 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42190/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 749eb3e..f388330 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -158,10 +158,7 @@ pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); - reg8 &= ~0x7; - reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ - pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
/* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); @@ -505,13 +502,9 @@
printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); - reg16 |= DEVEN_D1F0; - pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); + pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
- reg32 = pci_read_config32(p2peg, PEGCC); - reg32 &= ~(1 << 8); - pci_write_config32(p2peg, PEGCC, reg32); + pci_and_config32(p2peg, PEGCC, ~(1 << 8));
/* We have no success with querying the usual PCIe registers * for link setup success on the i945. Hence we assign a temporary @@ -531,16 +524,12 @@
pci_s_bridge_set_secondary(p2peg, tmp_secondary);
- reg32 = pci_read_config32(p2peg, 0x224); - reg32 &= ~(1 << 8); - pci_write_config32(p2peg, 0x224, reg32); + pci_and_config32(p2peg, 0x224, ~(1 << 8));
MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0));
/* Initialize PEG_CAP */ - reg16 = pci_read_config16(p2peg, PEG_CAP); - reg16 |= (1 << 8); - pci_write_config16(p2peg, PEG_CAP, reg16); + pci_or_config16(p2peg, PEG_CAP, 1 << 8);
/* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should be set from devicetree.cb. @@ -556,8 +545,7 @@ /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) - && --timeout) + while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) ;
reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); @@ -569,10 +557,7 @@
printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
- reg32 = pci_read_config32(p2peg, PEGSTS); - reg32 &= ~(0xf << 1); - reg32 |= 1; - pci_write_config32(p2peg, PEGSTS, reg32); + pci_update_config32(p2peg, PEGSTS, ~(0xf << 1), 1);
/* Force PCIRST# */ pci_s_assert_secondary_reset(p2peg); @@ -580,8 +565,7 @@
printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) - && --timeout) + while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) ;
reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); @@ -619,25 +603,17 @@ reg16 = (1 << 1); pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16);
- reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); - reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); - pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); + pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); }
- /* Enable GPEs */ - reg32 = pci_read_config32(p2peg, PEG_LC); - reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(p2peg, PEG_LC, reg32); + /* Enable GPEs: PMEGPE, HPGPE, GENGPE */ + pci_or_config32(p2peg, PEG_LC, (1 << 2) | (1 << 1) | (1 << 0));
/* Virtual Channel Configuration: Only VC0 on PCIe x16 */ - reg32 = pci_read_config32(p2peg, VC0RCTL); - reg32 &= 0xffffff01; - pci_write_config32(p2peg, VC0RCTL, reg32); + pci_and_config32(p2peg, VC0RCTL, ~0x000000fe);
/* Extended VC count */ - reg32 = pci_read_config32(p2peg, PVCCAP1); - reg32 &= ~(7 << 0); - pci_write_config32(p2peg, PVCCAP1, reg32); + pci_and_config32(p2peg, PVCCAP1, ~(7 << 0));
/* Active State Power Management ASPM */
@@ -653,35 +629,17 @@ pci_write_config32(p2peg, 0x228, 0xffffffff);
/* Program R/WO registers */ - reg32 = pci_read_config32(p2peg, 0x308); - pci_write_config32(p2peg, 0x308, reg32); - - reg32 = pci_read_config32(p2peg, 0x314); - pci_write_config32(p2peg, 0x314, reg32); - - reg32 = pci_read_config32(p2peg, 0x324); - pci_write_config32(p2peg, 0x324, reg32); - - reg32 = pci_read_config32(p2peg, 0x328); - pci_write_config32(p2peg, 0x328, reg32); + pci_update_config32(p2peg, 0x308, ~0, 0); + pci_update_config32(p2peg, 0x314, ~0, 0); + pci_update_config32(p2peg, 0x324, ~0, 0); + pci_update_config32(p2peg, 0x328, ~0, 0);
/* Additional PCIe graphics setup */ - reg32 = pci_read_config32(p2peg, 0xf0); - reg32 |= (3 << 26); - pci_write_config32(p2peg, 0xf0, reg32); + pci_or_config32(p2peg, 0xf0, 3 << 26); + pci_or_config32(p2peg, 0xf0, 3 << 24); + pci_or_config32(p2peg, 0xf0, 1 << 5);
- reg32 = pci_read_config32(p2peg, 0xf0); - reg32 |= (3 << 24); - pci_write_config32(p2peg, 0xf0, reg32); - - reg32 = pci_read_config32(p2peg, 0xf0); - reg32 |= (1 << 5); - pci_write_config32(p2peg, 0xf0, reg32); - - reg32 = pci_read_config32(p2peg, 0x200); - reg32 &= ~(3 << 26); - reg32 |= (2 << 26); - pci_write_config32(p2peg, 0x200, reg32); + pci_update_config32(p2peg, 0x200, ~(3 << 26), 2 << 26);
reg32 = pci_read_config32(p2peg, 0xe80); if (i945_silicon_revision() >= 2) @@ -690,13 +648,9 @@ reg32 &= ~(1 << 12); pci_write_config32(p2peg, 0xe80, reg32);
- reg32 = pci_read_config32(p2peg, 0xeb4); - reg32 &= ~(1 << 31); - pci_write_config32(p2peg, 0xeb4, reg32); + pci_and_config32(p2peg, 0xeb4, ~(1 << 31));
- reg32 = pci_read_config32(p2peg, 0xfc); - reg32 |= (1 << 31); - pci_write_config32(p2peg, 0xfc, reg32); + pci_or_config32(p2peg, 0xfc, 1 << 31);
if (i945_silicon_revision() >= 3) { static const u32 reglist[] = { @@ -705,12 +659,8 @@ };
int i; - for (i = 0; i < ARRAY_SIZE(reglist); i++) { - reg32 = pci_read_config32(p2peg, reglist[i]); - reg32 &= 0x0fffffff; - reg32 |= (2 << 28); - pci_write_config32(p2peg, reglist[i], reg32); - } + for (i = 0; i < ARRAY_SIZE(reglist); i++) + pci_update_config32(p2peg, reglist[i], ~(0xf << 28), 2 << 28); }
if (i945_silicon_revision() <= 2) { @@ -734,9 +684,7 @@ /* Toggle PCIRST# */ pci_s_assert_secondary_reset(p2peg);
- reg32 = pci_read_config32(p2peg, 0x224); - reg32 |= (1 << 8); - pci_write_config32(p2peg, 0x224, reg32); + pci_or_config32(p2peg, 0x224, 1 << 8);
pci_s_deassert_secondary_reset(p2peg);
@@ -751,9 +699,7 @@ printk(BIOS_DEBUG, "ok\n");
/* Finally: Disable the PCI config header */ - reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); - reg16 &= ~DEVEN_D1F0; - pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); + pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0); }
static void i945_setup_root_complex_topology(void) @@ -795,9 +741,7 @@ /* PCI Express x16 Port Root Topology */ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); - reg32 = pci_read_config32(p2peg, LE1D); - reg32 |= (1 << 0); - pci_write_config32(p2peg, LE1D, reg32); + pci_or_config32(p2peg, LE1D, 1 << 0); } }
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 34d129d..929968e 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -701,9 +701,7 @@ pci_write_config16(dev, GCFC, 0xa00); pci_write_config16(dev_host, GGC, (1 << 1));
- unsigned int reg32 = pci_read_config32(dev_host, DEVEN); - reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); - pci_write_config32(dev_host, DEVEN, reg32); + pci_and_config32(dev_host, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1));
dev->enabled = 0; } @@ -730,13 +728,8 @@
static void gma_func0_read_resources(struct device *dev) { - u8 reg8; - - /* Set Untrusted Aperture Size to 256mb */ - reg8 = pci_read_config8(dev, MSAC); - reg8 &= ~0x3; - reg8 |= 0x2; - pci_write_config8(dev, MSAC, reg8); + /* Set Untrusted Aperture Size to 256MB */ + pci_update_config8(dev, MSAC, ~0x3, 0x2);
pci_dev_read_resources(dev); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 4e3509e..b5444d1 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -257,9 +257,7 @@ }
/* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); - reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); + pci_or_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, 1 << 7);
/* clear self refresh status if check is disabled or not a resume */ if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) { @@ -1615,7 +1613,6 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) { u8 reg8; - u16 reg16; u8 freq, second_vco, voltage;
#define CRCLK_166MHz 0x00 @@ -1716,14 +1713,11 @@ sysinfo->clkcfg_bit7 = 0;
/* Graphics Core Render Clock */ - reg16 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC); - reg16 &= ~((7 << 0) | (1 << 13)); - reg16 |= freq; - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, reg16); + pci_update_config16(PCI_DEV(0, 2, 0), GCFC, ~((7 << 0) | (1 << 13)), freq);
/* Graphics Core Display Clock */ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC); - reg8 &= ~((1<<7) | (7<<4)); + reg8 &= ~((1 << 7) | (7 << 4));
if (voltage == VOLTAGE_1_05) { reg8 |= CDCLK_200MHz; @@ -1736,7 +1730,7 @@
reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1);
- reg8 |= (1<<3) | (1<<1); + reg8 |= (1 << 3) | (1 << 1); pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
reg8 |= 0x0f; @@ -1750,7 +1744,6 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) { u32 clkcfg; - u8 reg8; u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
printk(BIOS_DEBUG, "Setting Memory Frequency... "); @@ -1795,9 +1788,7 @@ /* Make sure the following code is in the cache before we execute it. */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); - reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7));
clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2142,7 +2133,6 @@
static void sdram_power_management(struct sys_info *sysinfo) { - u8 reg8; u16 reg16; u32 reg32; int integrated_graphics = 1; @@ -2293,13 +2283,9 @@ MCHBAR32(FSBPMC4) |= (1 << 4); }
- reg8 = pci_read_config8(PCI_DEV(0, 0x0, 0), 0xfc); - reg8 |= (1 << 4); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8); + pci_or_config8(PCI_DEV(0, 0x0, 0), 0xfc, 1 << 4);
- reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1); - reg8 |= (1 << 2); - pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); + pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2);
#ifdef C2_SELF_REFRESH_DISABLE
@@ -2729,7 +2715,6 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sys_info sysinfo; - u8 reg8;
timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); @@ -2826,9 +2811,7 @@ sdram_enable_rcomp();
/* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); - reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7));
printk(BIOS_DEBUG, "RAM initialization finished.\n");