Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6007
-gerrit
commit 01d40c6b6a5d4ce006183255df2ed0b7e3356212 Author: Stefan Reinauer reinauer@chromium.org Date: Wed Feb 19 15:05:15 2014 -0800
google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled"
Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer reinauer@google.com Signed-off-by: Stefan Reinauer reinauer@chromium.org Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: Stefan Reinauer reinauer@chromium.org Commit-Queue: Stefan Reinauer reinauer@chromium.org --- src/mainboard/google/panther/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 9fbe8e6..7cc3672 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/haswell register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V
+ # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + # Enable port coalescing register "pcie_port_coalesce" = "1"