[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/ramstage: Fix compilation issue

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46053 )

Change subject: soc/intel/alderlake/ramstage: Fix compilation issue
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Patch Set 1:

HI Angel, Tim,

Please consider my apology that I've missed rebasing ADL ramstage CL based on common code CLs hence it results into compilation issue.

Submitting this now. As we have mainboard code ready, hopefully won't rerepeat such mistake for ADL SoC.

Thanks,
Subrata