EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47286 )
Change subject: soc/intel/jasperlake: Enable Intel FIVR RFI settings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/ch... File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/ch... PS2, Line 360: Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% : * = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
These encodings are a little odd, adding an enum or #defines for those would be helpful to people se […]
I think this can change to the FSP comment: # !BSF NAME:{FIVR RFI Spread Spectrum} # !BSF TYPE:{EditNum, HEX, (0x0,0xFF)} # !BSF HELP:{PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>; Range: 0.0% to 10.0% (0-100).} gPlatformFspPkgTokenSpaceGuid.FivrSpreadSpectrum | * | 0x01 | 0x00
This is clear 0.1 increments.