[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40840

to look at the new patch set (#3).

Change subject: soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register
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soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/jasperlake/bootblock/pch.c
1 file changed, 5 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40840/3