Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35440 )
Change subject: intel/ibexpeak boards: Remove handled RCBA entries from replay ......................................................................
intel/ibexpeak boards: Remove handled RCBA entries from replay
The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those.
The remainder now consist of USB setup and undocumented bits that should likely not be touched at all.
Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/35440 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 20 insertions(+), 36 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 9d98637..1d364b6 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -65,23 +65,15 @@ { southbridge_configure_default_intmap();
+ /* Must set BIT0 (hides performance counters PCI device). + coreboot enables the Rate Matching Hub which makes the UHCI PCI + devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ + RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; + static const u32 rcba_dump3[] = { - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, @@ -120,8 +112,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3400) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3400); + RCBA32(4 * i + 0x3500) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3500); } }
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a426d89..00461a1 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -60,23 +60,15 @@ { southbridge_configure_default_intmap();
+ /* Must set BIT0 (hides performance counters PCI device). + coreboot enables the Rate Matching Hub which makes the UHCI PCI + devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ + RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; + static const u32 rcba_dump3[] = { - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, @@ -116,8 +108,8 @@ unsigned i;
for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3400) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3400); + RCBA32(4 * i + 0x3500) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3500); } }