[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Pass MISCCFG.bit 0-5 devicetree.cb to ASL

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37794 )

Change subject: soc/intel/cannonlake: Pass MISCCFG.bit 0-5 devicetree.cb to ASL
......................................................................

soc/intel/cannonlake: Pass MISCCFG.bit 0-5 devicetree.cb to ASL

This patch performs below operations:
1. Refactor soc_gpio_pm_configuration() and create new API
to fill gpio pm configuration as in fill_soc_gpio_pm_configuration()
2. Pass GPIO PM configuration values between devicetree.cb to platform
ASL

Now SoC code should be able to handle dynamic GPIO PM programming through
ACPI/ASL

BUG=b:144002424
TEST=Verify devicetree.cb gpio_pm[] variables and GPMx ASL variables are
in sync.

Change-Id: I75246be01aa4ab4cfa1e184ab6a11b718471995e
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/gpio_common.c
M src/soc/intel/cannonlake/include/soc/gpio.h
3 files changed, 21 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37794/1

diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 6846594..31e3227 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -233,6 +233,10 @@
    /* Set USB2/USB3 wake enable bitmaps. */
    gnvs->u2we = config->usb2_wake_enable_bitmap;
    gnvs->u3we = config->usb3_wake_enable_bitmap;
+
+	/* Fill SoC GPIO PM configuration */
+	gnvs->ogpm = config->gpio_override_pm;
+	fill_soc_gpio_pm_configuration(gnvs->gpmv, TOTAL_GPIO_COMM);
 }

uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c
index 360189a..b6ed74a 100644
--- a/src/soc/intel/cannonlake/gpio_common.c
+++ b/src/soc/intel/cannonlake/gpio_common.c
@@ -17,6 +17,18 @@
 #include <intelblocks/gpio.h>
 #include <soc/soc_chip.h>

+/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
+void fill_soc_gpio_pm_configuration(uint8_t *misccfg_pm_values, size_t size)
+{
+	const config_t *config = config_of_soc();
+
+	if (config->gpio_override_pm)
+		memcpy(misccfg_pm_values, config->gpio_pm, sizeof(uint8_t) * size);
+	else
+		memset(misccfg_pm_values, MISCCFG_ENABLE_GPIO_PM_CONFIG,
+				sizeof(uint8_t) * size);
+}
+
 /*
  * Routine to perform below operations:
  * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register
@@ -25,14 +37,8 @@
 void soc_gpio_pm_configuration(void)
 {
    uint8_t value[TOTAL_GPIO_COMM];
-	const config_t *config = config_of_soc();

-	if (config->gpio_override_pm)
-		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
-				TOTAL_GPIO_COMM);
-	else
-		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
-				TOTAL_GPIO_COMM);
+	fill_soc_gpio_pm_configuration(value, TOTAL_GPIO_COMM);

gpio_pm_configure(value, TOTAL_GPIO_COMM);
 }
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index efed881..0625c63 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -26,8 +26,12 @@
 #include <intelblocks/gpio.h>

#ifndef __ACPI__
+#include <stdint.h>
 struct pad_config;
 void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads);
+
+/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
+void fill_soc_gpio_pm_configuration(uint8_t *misccfg_pm_values, size_t size);
 /*
  * Routine to perform below operations:
  * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register